Integrated VLSI layout compaction and wire balancing on a shared memory multiprocessor: evaluation of a parallel algorithm

We first present a unged formulation to three problems in VLSI physical design: Layout compaction, Wire balancing and Integrated layout compaction and wire balancing problems. The aim of layout compaction is to achieve minimum chip width. Whereas wire balancing seeks to achieve minimum total wire length, integrated layout compaction and wire balancing seeks to minimize wire length maintaining the chip width at the optimum value. Our formulation is in terms of the dual transshipment problem We then review our recent work on a parallel algorithm for the dual transshipment problem We show how this algorithm called Modified Network Dual Simplex Method provides a unified approach to solve the three problems mentioned above and present experimental results. Our implementations have been on the BBN Bunerjly machine. We draw attention to certain rather unusual results and argue that if the MNDS method is used, then integrated layout compaction and wire balancing will achieve minimum chip width and a total wire length close to the optimum achieved by the wire balancing algorithm.